sort-as to some PORT entries

shidel · shidel · commit 41559cbf5b83 · 2026-04-17T11:16:44.000-04:00
diff --git a/source/Ports List/PORT 002E002F DELL ENHANCED PARALLEL PORT.txt b/source/Ports List/PORT 002E002F DELL ENHANCED PARALLEL PORT.txt
@@ -1,5 +1,6 @@
 --------------------------------------------------------------------------------
  Unique ID: P002E002F
+   Sort As: P002E002F+01
   Category: - 	reserved (and not otherwise classified)
       Flag: n/a
 --------------------------------------------------------------------------------
@@ -15,4 +16,4 @@ Values for Dell Enhanced Parallel Port register index:
  00h	bit 0: ???
  02h	bit 7: port in bidirectional mode
  04h	bits 0 and 2: ECP/EPP mode control
-
+
diff --git a/source/Ports List/PORT 002E002F Intel Nonolet Motherboard POWER MANAGEMENT.txt b/source/Ports List/PORT 002E002F Intel Nonolet Motherboard POWER MANAGEMENT.txt
@@ -1,5 +1,6 @@
 --------------------------------------------------------------------------------
  Unique ID: P002E002F
+   Sort As: P002E002F+02
   Category: - 	reserved (and not otherwise classified)
       Flag: n/a
 --------------------------------------------------------------------------------
@@ -16,4 +17,4 @@ code sequence posted in fido7.nice.sources by Konstantin Mohorea:
      out 2Fh,00h
      out 2Eh,0Dh
      out 2Fh,A0h
-
+
diff --git a/source/Ports List/PORT 002E002F NS PC87306 SuperI O CONFIGURATION REGISTERS.txt b/source/Ports List/PORT 002E002F NS PC87306 SuperI O CONFIGURATION REGISTERS.txt
@@ -1,5 +1,6 @@
 --------------------------------------------------------------------------------
  Unique ID: P002E002F
+   Sort As: P002E002F+03
   Category: - 	reserved (and not otherwise classified)
       Flag: n/a
 --------------------------------------------------------------------------------
@@ -15,4 +16,4 @@ Note:	to set a register, the data port must be written twice in a row; the
 
 002E  RW  configuration register index
 002F  RW  configuration register data
-
+
diff --git a/source/Ports List/PORT 72EE ATI Mach8 Mach32 BOUNDS ACCUMULATOR LEFT.txt b/source/Ports List/PORT 72EE ATI Mach8 Mach32 BOUNDS ACCUMULATOR LEFT.txt
@@ -1,5 +1,6 @@
 --------------------------------------------------------------------------------
  Unique ID: P72EE
+   Sort As: P72EE+01
   Category: V 	video
       Flag: n/a
 --------------------------------------------------------------------------------
@@ -8,4 +9,4 @@ PORT 72EE - ATI Mach8/Mach32 - BOUNDS ACCUMULATOR (LEFT)
 SeeAlso: PORT 76EEh"BOUNDS",PORT 7AEEh"BOUNDS",PORT 7EEEh"BOUNDS"
 
 72EEw R-  left edge of bounding box for points written via Line Draw register
-
+
diff --git a/source/Ports List/PORT 72EE ATI Mach8 Mach32 ENGINE VIDEO BUFFER OFFSET HIGH.txt b/source/Ports List/PORT 72EE ATI Mach8 Mach32 ENGINE VIDEO BUFFER OFFSET HIGH.txt
@@ -1,5 +1,6 @@
 --------------------------------------------------------------------------------
  Unique ID: P72EE
+   Sort As: P72EE+02
   Category: V 	video
       Flag: n/a
 --------------------------------------------------------------------------------
@@ -10,4 +11,4 @@ SeeAlso: PORT 6EEEh
 72EE  -W  high bits of video buffer starting offset
 		bits 1-0 for Mach-8
 		bits 3-0 for Mach-32
-
+
diff --git a/source/Ports List/PORT 76EE ATI Mach8 Mach32 BOUNDS ACCUMULATOR TOP.txt b/source/Ports List/PORT 76EE ATI Mach8 Mach32 BOUNDS ACCUMULATOR TOP.txt
@@ -1,5 +1,6 @@
 --------------------------------------------------------------------------------
  Unique ID: P76EE
+   Sort As: P76EE+01
   Category: V 	video
       Flag: n/a
 --------------------------------------------------------------------------------
@@ -8,4 +9,4 @@ PORT 76EE - ATI Mach8/Mach32 - BOUNDS ACCUMULATOR (TOP)
 SeeAlso: PORT 72EEh"BOUNDS",PORT 7AEEh"BOUNDS",PORT 7EEEh"BOUNDS"
 
 76EEw R-  top edge of bounding box for points written via Line Draw register
-
+
diff --git a/source/Ports List/PORT 76EE ATI Mach8 Mach32 ENGINE DISPLAY PITCH.txt b/source/Ports List/PORT 76EE ATI Mach8 Mach32 ENGINE DISPLAY PITCH.txt
@@ -1,5 +1,6 @@
 --------------------------------------------------------------------------------
  Unique ID: P76EE
+   Sort As: P76EE+02
   Category: V 	video
       Flag: n/a
 --------------------------------------------------------------------------------
@@ -8,4 +9,4 @@ PORT 76EE - ATI Mach8/Mach32 - ENGINE DISPLAY PITCH
 SeeAlso: PORT 6AEEh,PORT 7AEEh
 
 76EE  -W  display pitch
-
+
diff --git a/source/Ports List/PORT 7AEE ATI Mach8 Mach32 BOUNDS ACCUMULATOR RIGHT.txt b/source/Ports List/PORT 7AEE ATI Mach8 Mach32 BOUNDS ACCUMULATOR RIGHT.txt
@@ -1,5 +1,6 @@
 --------------------------------------------------------------------------------
  Unique ID: P7AEE
+   Sort As: P7AEE+01
   Category: V 	video
       Flag: n/a
 --------------------------------------------------------------------------------
@@ -8,4 +9,4 @@ PORT 7AEE - ATI Mach8/Mach32 - BOUNDS ACCUMULATOR (RIGHT)
 SeeAlso: PORT 72EEh"BOUNDS",PORT 76EEh"BOUNDS",PORT 7EEEh"BOUNDS"
 
 7AEEw R-  right edge of bounding box for points written via Line Draw register
-
+
diff --git a/source/Ports List/PORT 7AEE ATI Mach8 Mach32 EXTENDED GRAPHICS ENGINE CONGIFURATION.txt b/source/Ports List/PORT 7AEE ATI Mach8 Mach32 EXTENDED GRAPHICS ENGINE CONGIFURATION.txt
@@ -1,5 +1,6 @@
 --------------------------------------------------------------------------------
  Unique ID: P7AEE
+   Sort As: P7AEE+02
   Category: V 	video
       Flag: n/a
 --------------------------------------------------------------------------------
@@ -32,4 +33,4 @@ Bit(s)	Description	(Table P1025)
 	11 twenty-four
  3	report monitor alias instead of actual monitor
  2-0	alternate monitor ID (alias)
-
+
diff --git a/source/Ports List/PORT 83C683C9 Chips Technologies 64200 Wingine DAC color registers.txt b/source/Ports List/PORT 83C683C9 Chips Technologies 64200 Wingine DAC color registers.txt
@@ -1,5 +1,6 @@
 --------------------------------------------------------------------------------
  Unique ID: P83C683C9
+   Sort As: P83C683C9+01
   Category: V 	video
       Flag: n/a
 --------------------------------------------------------------------------------
@@ -12,4 +13,4 @@ SeeAlso: PORT 03C6h
 83C7  -W  color palette read-mode index
 83C8  RW  color palette write-mode index
 83C9  RW  color palette data (three bytes)
-
+
diff --git a/source/Ports List/PORT 83C683C9 Compaq Qvision EISA DAC color registers.txt b/source/Ports List/PORT 83C683C9 Compaq Qvision EISA DAC color registers.txt
@@ -1,9 +1,10 @@
 --------------------------------------------------------------------------------
  Unique ID: P83C683C9
+   Sort As: P83C683C9+02
   Category: V 	video
       Flag: n/a
 --------------------------------------------------------------------------------
 
 PORT 83C6-83C9 - Compaq Qvision EISA - DAC color registers
 SeeAlso: PORT 03C6h
-
+
diff --git a/source/Ports List/PORT xxxx AMD Am53C974A PCSCSI II SCSI adapter.txt b/source/Ports List/PORT xxxx AMD Am53C974A PCSCSI II SCSI adapter.txt
@@ -1,5 +1,6 @@
 --------------------------------------------------------------------------------
  Unique ID: Pxxxx
+   Sort As: Pxxxx+03
   Category: d 	disk I/O enhancements
       Flag: n/a
 --------------------------------------------------------------------------------
@@ -44,4 +45,4 @@ Notes:	the SCSI registers are mapped on DWORD boundaries, even though for most
 	  only the least-significant byte is used
 	see "Am53C974A PCscsi(tm) II Technical Manual, Revision 1.0"
 	  (file 19113A.PDF) for further details, as well as (file 19084A.PDF)
-
+
diff --git a/source/Ports List/PORT xxxx AMD645 Power Management Registers.txt b/source/Ports List/PORT xxxx AMD645 Power Management Registers.txt
@@ -1,5 +1,6 @@
 --------------------------------------------------------------------------------
  Unique ID: Pxxxx
+    Sort As: Pxxxx+04
   Category: p 	power management
       Flag: n/a
 --------------------------------------------------------------------------------
@@ -271,4 +272,4 @@ Bit(s)	Description	(Table P1075)
  1	GPIO1 input value
  0	GPIO0 input value
 SeeAlso: #P1074
-
+
diff --git a/source/Ports List/PORT xxxx AMD645 USB.txt b/source/Ports List/PORT xxxx AMD645 USB.txt
@@ -1,5 +1,6 @@
 --------------------------------------------------------------------------------
  Unique ID: Pxxxx
+    Sort As: Pxxxx+05
   Category: X 	expansion bus BIOSes
       Flag: n/a
 --------------------------------------------------------------------------------
@@ -17,4 +18,4 @@ Note:	further details are supposedly in the UHCI v1.1 standard
 +00D	unused???
 +010w RW  Port 1 Status/Control
 +012w RW  Port 2 Status/Control
-
+
diff --git a/source/Ports List/PORT xxxx Adaptec AHA2920 PCI SCSI adapter.txt b/source/Ports List/PORT xxxx Adaptec AHA2920 PCI SCSI adapter.txt
@@ -1,5 +1,6 @@
 --------------------------------------------------------------------------------
  Unique ID: Pxxxx
+   Sort As: Pxxxx+01
   Category: d 	disk I/O enhancements
       Flag: n/a
 --------------------------------------------------------------------------------
@@ -10,4 +11,4 @@ Note:	Adaptec AHA-2920 PCI SCSI adapter is based upon Future Domain TMC-36C70
 	  SCSI controller which is a PCI version of Future Domain TMC-18C30 ISA
 	  SCSI controller
 SeeAlso: PORT 0140h-014Fh"Future Domain TMC-16x0"
-
+
diff --git a/source/Ports List/PORT xxxx Adaptec AIC78xx PCI SCSI controller.txt b/source/Ports List/PORT xxxx Adaptec AIC78xx PCI SCSI controller.txt
@@ -1,5 +1,6 @@
 --------------------------------------------------------------------------------
  Unique ID: Pxxxx
+   Sort As: Pxxxx+02
   Category: d 	disk I/O enhancements
       Flag: n/a
 --------------------------------------------------------------------------------
diff --git a/source/Ports List/PORT xxxx Ensoniq AudioPCI ES1370 CONTROL REGISTERS.txt b/source/Ports List/PORT xxxx Ensoniq AudioPCI ES1370 CONTROL REGISTERS.txt
@@ -1,5 +1,6 @@
 --------------------------------------------------------------------------------
  Unique ID: Pxxxx
+   Sort As: Pxxxx+06
   Category: - 	reserved (and not otherwise classified)
       Flag: n/a
 --------------------------------------------------------------------------------
@@ -376,4 +377,4 @@ Bit(s)	Description	(Table P1088)
  7-0	UART data received through MIDI interface
 ------
 SeeAlso: #P1087
-
+
diff --git a/source/Ports List/PORT xxxx Ensoniq AudioPCI97 ES1371 CONTROL REGISTERS.txt b/source/Ports List/PORT xxxx Ensoniq AudioPCI97 ES1371 CONTROL REGISTERS.txt
@@ -1,5 +1,6 @@
 --------------------------------------------------------------------------------
  Unique ID: Pxxxx
+   Sort As: Pxxxx+07
   Category: - 	reserved (and not otherwise classified)
       Flag: n/a
 --------------------------------------------------------------------------------
@@ -100,4 +101,4 @@ Bit(s)	Description	(Table P1091)
 	0 = interrupt occurred
 	0 = interrupt not occurred
 Note:	this register is addressable as byte, word and dword
-
+
diff --git a/source/Ports List/PORT xxxx Future Domain TMC3260 PCI SCSI adapter.txt b/source/Ports List/PORT xxxx Future Domain TMC3260 PCI SCSI adapter.txt
@@ -1,5 +1,6 @@
 --------------------------------------------------------------------------------
  Unique ID: Pxxxx
+   Sort As: Pxxxx+08
   Category: d 	disk I/O enhancements
       Flag: n/a
 --------------------------------------------------------------------------------
@@ -10,4 +11,4 @@ Note:	Future Domain TMC-3260 PCI SCSI adapter is based upon Future Domain
 	  TMC-36C70 SCSI controller which is a PCI version of the TMC-18C30
 	  ISA SCSI controller
 SeeAlso: PORT 0140h-014Fh"Future Domain TMC-16x0"
-
+
diff --git a/source/Ports List/PORT xxxx Intel 82371 OPTi Vendetta 82C750 Bus Master IDE Registers.txt b/source/Ports List/PORT xxxx Intel 82371 OPTi Vendetta 82C750 Bus Master IDE Registers.txt
@@ -1,5 +1,6 @@
 --------------------------------------------------------------------------------
  Unique ID: Pxxxx
+   Sort As: Pxxxx+09
   Category: d 	disk I/O enhancements
       Flag: n/a
 --------------------------------------------------------------------------------
@@ -46,4 +47,4 @@ Bit(s)	Description	(Table P1094)
 Notes:	(Intel 82371) the descriptor table must not cross a 4K boundary
 	(OPTi "Vendetta") the descriptor table must not cross a 64K boundary
 SeeAlso: #P1092,#P1093
-
+
diff --git a/source/Ports List/PORT xxxx Intel 82371SB USB Host I O Registers.txt b/source/Ports List/PORT xxxx Intel 82371SB USB Host I O Registers.txt
@@ -1,5 +1,6 @@
 --------------------------------------------------------------------------------
  Unique ID: Pxxxx
+   Sort As: Pxxxx+10
   Category: - 	reserved (and not otherwise classified)
       Flag: n/a
 --------------------------------------------------------------------------------
@@ -87,4 +88,4 @@ Bit(s)	Description	(Table P1100)
  0	current connect status (read-only)
 Note:	only WORD writes are permitted to this register
 SeeAlso: #P1095
-
+
