added sort-as to some MSR entries

Author: shidel

source/Model-Specific Registers/MSR 00000003h Cyrix 6x86MX TEST DATA.txt

@@ -1,5 +1,5 @@
 --------------------------------------------------------------------------------
- Unique ID: S00000003
+ Unique ID: S00000003-sort-as-S0000000302
   Category: - 	reserved (and not otherwise classified)
       Flag: n/a
 --------------------------------------------------------------------------------
@@ -12,4 +12,4 @@ Bit(s)	Description	(Table R0062)
  63-32	reserved
  31-0	cache data, similar to that for Pentium TR3 (see #R0004)
 SeeAlso: #R0004,#R0063,#R0064
-
+

source/Model-Specific Registers/MSR 00000003h Pentium INVALID.txt

@@ -1,10 +1,10 @@
 --------------------------------------------------------------------------------
- Unique ID: S00000003
+ Unique ID: S00000003-sort-as-S0000000301
   Category: - 	reserved (and not otherwise classified)
       Flag: n/a
 --------------------------------------------------------------------------------
 
 MSR 00000003h - Pentium - INVALID
 Note:	attempted accesses to this MSR cause an exception
 SeeAlso: MSR 80000003h,MSR 0000000Fh
-
+

source/Model-Specific Registers/MSR 00000004h Cyrix 6x86MX TEST ADDRESS.txt

@@ -1,5 +1,5 @@
 --------------------------------------------------------------------------------
- Unique ID: S00000004
+ Unique ID: S00000004-sort-as-S0000000402
   Category: - 	reserved (and not otherwise classified)
       Flag: n/a
 --------------------------------------------------------------------------------
@@ -12,4 +12,4 @@ Bit(s)	Description	(Table R0063)
  63-32	reserved
  31-0	cache address, like Pentium TR4 (see #R0005)
 SeeAlso: #R0062,#R0064
-
+

source/Model-Specific Registers/MSR 00000004h Pentium TR2 INSTRUCTION CACHE END BITS.txt

@@ -1,5 +1,5 @@
 --------------------------------------------------------------------------------
- Unique ID: S00000004
+ Unique ID: S00000004-sort-as-S0000000401
   Category: - 	reserved (and not otherwise classified)
       Flag: n/a
 --------------------------------------------------------------------------------
@@ -19,4 +19,4 @@ Note:	when a new line is written into the code cache, all end bits are set;
 	  the instruction decoder then clears those bits corresponding to
 	  bytes which are not the last byte of an instruction
 SeeAlso: #R0004
-
+

source/Model-Specific Registers/MSR 00000005h Cyrix 6x86MX TEST COMMAND STATUS.txt

@@ -1,5 +1,5 @@
 --------------------------------------------------------------------------------
- Unique ID: S00000005
+ Unique ID: S00000005-sort-as-S0000000502
   Category: - 	reserved (and not otherwise classified)
       Flag: n/a
 --------------------------------------------------------------------------------
@@ -34,4 +34,4 @@ Bit(s)	Description	(Table R0064)
 	10 read cache
 	11 no cache or test register modification
 SeeAlso: #R0062,#R0063
-
+

source/Model-Specific Registers/MSR 00000005h Pentium TR3 CACHE DATA TEST REGISTER.txt

@@ -1,5 +1,5 @@
 --------------------------------------------------------------------------------
- Unique ID: S00000005
+ Unique ID: S00000005-sort-as-S0000000501
   Category: - 	reserved (and not otherwise classified)
       Flag: n/a
 --------------------------------------------------------------------------------
@@ -14,4 +14,4 @@ Bit(s)	Description	(Table R0004)
  63-32	reserved (0)
  31-0	data read/written from/to cache (code or data)
 SeeAlso: #R0005,#R0062
-
+

source/Model-Specific Registers/MSR 0000008Bh Pentium Pro BIOS SIGN BIOS UPDATE SIGNATURE.txt

@@ -1,5 +1,5 @@
 --------------------------------------------------------------------------------
- Unique ID: S0000008B
+ Unique ID: S0000008B-sort-as-S0000008B01
   Category: - 	reserved (and not otherwise classified)
       Flag: n/a
 --------------------------------------------------------------------------------
@@ -18,4 +18,4 @@ Notes:	whenever a microcode update is loaded, the PentiumPro modifies the
 	  standard model/stepping information, while the high 32 bits contain
 	  the microcode update ID
 SeeAlso: MSR 00000079h
-
+

source/Model-Specific Registers/MSR 0000008Bh PentiumII BBL CR D3 CHUNK 3 DATA REGISTER.txt

@@ -1,5 +1,5 @@
 --------------------------------------------------------------------------------
- Unique ID: S0000008B
+ Unique ID: S0000008B-sort-as-S0000008B02
   Category: - 	reserved (and not otherwise classified)
       Flag: n/a
 --------------------------------------------------------------------------------
@@ -9,4 +9,4 @@ Notes:	this register is used to read from and write to L2 cache
 	whether this MSR is the BIOS update signature or L2 data depends on
 	  the usage model
 SeeAlso: MSR 00000088h,MSR 00000089h,MSR 00000116h
-
+