This is a WIP SystemVerilog project for developing a scalable, parameterised and piplined set of modules to constrct a 1-D convolutional neural network able to be synthesised in hardware on the Intel MAX 10 series of FPGAs.
1dcnn
├───ip
├───matlab
├───pkg
├───python
├───quartus
├───samples
│ └───original
├───src
├───test
│ ├───modelsim
│ ├───samples
│ └───weights
├───top
└───weights
└───latest
| File | Description |
|---|---|
| ip | MAX 10 Intel megafunction IP for DSP blocks such as multipliers or dividers (generated by quartus) |
| pkg | Package files for helpful functions and helpful parameters |
| python | Python scripts |
| quartus | Quartus project |
| samples | Sample data used for testing, simulations and pre-training the network |
| src | Neural network coponents source Verilog |
| test | Testbenches for source Verilog |
| top | Top-level source files for full networks (e.g., XOR) |
| weights | Weights and biases pre-generated by the MATLAB network in .csv format |