Electronics and Instrumentation Engineering undergraduate interested in Analog & Mixed-Signal VLSI, Low-Power CMOS Design, SAR ADC architectures, FPGA systems, and hardware-oriented research.
- CGPA: 9.34
- GATE 2026 (IN): AIR 776 | Score 527
- GATE 2026 (EC): AIR 4835 | Score 499
- 12-bit Asynchronous SAR ADC in 45 nm CMOS
- Low-power mixed-signal circuit design
- Timing analysis and transistor-level optimization
- Analog & Mixed-Signal IC Design
- Low-Power CMOS Circuits
- SAR ADC Architectures
- Dynamic Comparators
- Digital VLSI
- FPGA Systems
- Embedded Systems
- Low-Power TSPC D Flip-Flop in 45 nm CMOS
- 6-bit Sequential Adder on FPGA
- Adaptive FIR Audio Enhancement
- Boost Converter with Feedforward Control
- Hybrid Low-Light Image Enhancement
- LTspice
- Electric VLSI
- Verilog HDL
- Xilinx Vivado
- MATLAB / Simulink
- C / C++
- Git & GitHub
- ISWDP Level 1 — IISc Bangalore & Samsung Semiconductor
- VLSI Circuits and Systems (Analog & Digital) — IIT Kharagpur
- Real-Time Digital Signal Processing — NPTEL (IISc Bangalore)
- LinkedIn: https://www.linkedin.com/in/sriti-sancharika-a09354260
- ORCID: https://orcid.org/0009-0003-5934-7762
⭐ Interested in low-power mixed-signal systems, CMOS circuit design, and hardware-oriented research.