Preparing to release v0.6.10 - #690
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desmonddak
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Jul 31, 2026
desmonddak
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desmonddak
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Jul 31, 2026
| - Added per-direction configuration of explicit or implicit object and data types for generated SystemVerilog ports. Defaults preserve the existing `input logic`, `output logic`, and `inout wire` declarations (<https://github.com/intel/rohd/pull/678>). | ||
| - Added per-direction configuration of explicit or implicit object and data types for generated SystemVerilog ports. Defaults preserve the existing `input logic`, `output logic`, and `inout wire` declarations (<https://github.com/intel/rohd/pull/678>, <https://github.com/intel/rohd/pull/687>). | ||
| - Significantly enhanced ROHD DevTools with embedded and standalone VM connections, live hierarchy and signal inspection, filtering, snapshots and export, and cross-probe integration (<https://github.com/intel/rohd/pull/665>). | ||
| - Improved `Logic.getRange` and `slice` on filled `Const`s to return direct constants instead of constructing `BusSubset` modules (<https://github.com/intel/rohd/pull/677>). |
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- Significantly enhanced ROHD DevTools with embedded and standalone VM connections, live hierarchy and signal inspection, filtering, snapshots and export, and cross-probe integration (Devtools #665).
- Added the
rohd_hierarchypackage for compact hierarchy dictionaries, canonical occurrence addresses, hierarchy search, and netlist adapters (ROHD Hierarchy: an API for compact, generic traversal of a remote design #653). - Added the ROHD VS Code extension with context-aware snippets, Dart Tooling Daemon integration, and source navigation for cross-probing from ROHD viewers (Rohd extension #670).
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Description & Motivation
Preparations to release v0.6.10
Also adding a script to make releases easier