Pinned Loading

1. Deeploy Deeploy Public

   DNN Compiler for Heterogeneous SoCs

   Python 71 46

2. carfield carfield Public

   A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.

   Tcl 127 33

3. cheshire cheshire Public

   A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

   Verilog 352 113

4. snitch_cluster snitch_cluster Public

   An energy-efficient RISC-V floating-point compute cluster.

   C 138 111

5. axi axi Public

   AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

   SystemVerilog 1.6k 360

6. ara ara Public

   The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

   C 530 190