[ExecuTorch][WebGPU] Add max_pool2d op

[JCNTH]

Stack from ghstack (oldest at bottom):

• [ExecuTorch][WebGPU] apply_rotary_emb_hf op tests #20876
• [ExecuTorch][WebGPU] et_vk.apply_rotary_emb_hf: HuggingFace rotate-half RoPE runtime op (unblocks Qwen3) #20875
• [ExecuTorch][WebGPU] et_vk conv2d im2col-GEMM tests #20874
• [ExecuTorch][WebGPU] et_vk conv2d: route standard (groups==1) conv through an im2col tiled GEMM (1.1-2.4x) #20873
• [ExecuTorch][WebGPU] et_vk.sdpa channel-attention tests #20872
• [ExecuTorch][WebGPU] et_vk.sdpa: shape-route QK to a per-entry kernel for channel attention (15-30x faster) #20871
• [ExecuTorch][WebGPU] Migrate quantized_linear to make_compute_pipeline #20870
• [ExecuTorch][WebGPU] Migrate multi-dispatch ops to make_compute_pipeline #20869
• [ExecuTorch][WebGPU] Migrate 9 ops to make_compute_pipeline (layout:"auto") #20868
• [ExecuTorch][WebGPU] Adopt WebGPU layout:"auto" in make_compute_pipeline #20867
• [ExecuTorch][WebGPU] slice_copy native golden test #20866
• [ExecuTorch][WebGPU] slice_copy Double-arg scalar handling + view_copy/alias glue #20865
• [ExecuTorch][WebGPU] relu op tests #20864
• [ExecuTorch][WebGPU] Add relu op (shared unary handler; sigmoid adopts make_compute_pipeline) #20863
• [ExecuTorch][WebGPU] max_pool2d op tests #20862
• -> [ExecuTorch][WebGPU] Add max_pool2d op #20861
• [ExecuTorch][WebGPU] upsample_nearest2d op tests #20860
• [ExecuTorch][WebGPU] Add upsample_nearest2d op #20859
• [ExecuTorch][WebGPU] constant_pad_nd op tests #20858
• [ExecuTorch][WebGPU] Add constant_pad_nd op #20857
• [ExecuTorch][WebGPU] addmm op tests #20856
• [ExecuTorch][WebGPU] Add optimized addmm op #20855
• [ExecuTorch][WebGPU] embedding op tests #20854
• [ExecuTorch][WebGPU] Add embedding op #20853
• [ExecuTorch][WebGPU] SDPA op tests #20852
• [ExecuTorch][WebGPU] Add optimized SDPA op #20851
• [ExecuTorch][WebGPU] conv2d op tests #20850
• [ExecuTorch][WebGPU] Add optimized conv2d op #20849
• [ExecuTorch][WebGPU] linear_fp32 op tests #20848
• [ExecuTorch][WebGPU] Add optimized linear_fp32 op #20847
• [ExecuTorch][WebGPU] layer_norm op tests #20846
• [ExecuTorch][WebGPU] Add optimized layer_norm op #20845
• [ExecuTorch][WebGPU] gelu op tests #20844
• [ExecuTorch][WebGPU] Add optimized gelu op #20843
• [ExecuTorch][WebGPU] Shared pipeline + dispatch-grid + vec4-align helpers (op-suite foundation) #20842

Adds aten.max_pool2d_with_indices.default to the WebGPU backend, enabling the SAM2 Hiera q_pool path (values, with optional indices).

Problem — max pooling (F.max_pool2d, which decomposes to max_pool2d_with_indices) had no WebGPU kernel, blocking the SAM2 Hiera q_pool downsampling stages.

Solution — Before — no handler; the multi-output max_pool2d_with_indices unsupported. After — one thread per output element (n, c, oh, ow) gathers its pooling window and writes the max (and, when the graph requests them, the argmax indices).

Implementation:

• The kernel iterates the kH x kW window with general stride/padding/dilation, skips out-of-range (padding) cells, and tracks the running max; best initialises to -3.4e38 (a large finite negative, because Dawn/Tint rejects the exact -FLT_MAX literal).
• Argmax is ALWAYS tracked; a write_indices override (a compile-time spec constant) gates only the final out_idx store, so the values-only and with-indices paths run one shader and stay bit-identical on out_vals. Indices are the flat ih*IW+iw spatial-plane offset (matching torch.nn.functional.max_pool2d(return_indices=True), not an absolute NCHW offset).
• The out is a ValueList [values, indices]; when indices are not requested the handler binds a tiny dummy storage buffer to slot 3 (the shader never writes it) rather than allocating a real indices tensor — mirroring the dummy_affine pattern in NativeLayerNorm.cpp. When indices ARE requested it validates that the indices tensor is int32 (4 bytes/elem) and shares the values shape, else throws (the kernel writes i32, so an int64 indices tensor would mis-stride the write).
• The handler parses kernel_size/stride/padding/dilation via utils::parse_hw (a single value broadcasts to both spatial dims; stride defaults to kernel_size when empty), derives OH/OW from the pooling formula, and validates them against the serialized values output (loud-fail on a ceil_mode / layout mismatch).
• Adaptive 1D->2D dispatch via utils::compute_dispatch_grid.
• Mirrors Vulkan backends/vulkan/runtime/graph/ops/impl/Pool.cpp (the ValueList[values, indices] shape, the write_indices spec constant, unconditional argmax tracking, and 32-bit indices despite ATen's int64 schema).

Constraints — fp32 values; 4D NCHW; general kernel/stride/padding/dilation; ceil_mode unsupported (the output-shape validation assumes floor); the optional indices output must be int32; the output element count must fit u32.

Co-authored-with: Claude Code.

Differential Revision: D110836680

[pytorch-bot]

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✅ You can merge normally! (1 Unrelated Failure)

As of commit 4f64523 with merge base aceeb40 ():

BROKEN TRUNK - The following job failed but were present on the merge base:

👉 Rebase onto the `viable/strict` branch to avoid these failures

• pull / unittest-nxp-neutron / linux-job (gh) (trunk failure)
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