Image Processing Toolbox in Verilog using Basys3 FPGA

A Single Cycle Risc-V 32 bit CPU

Single Cycle 32 bit MIPS

👻 Simple Undertale-like game on Basys3 FPGA written in Verilog

Digital Systems Course Project: Fake Currency Detection in Verilog using Basys3 FPGA and MATLAB

Cache Controller for a multi-level Cache memory using four-way set-associative mapping with write-back, no-write allocate and LRU policy. Implemented on a Basys3 Artix-7 FPGA with proper delays and hit signals.

Digital clock implemented in vhdl for the Basys 3 Board from Digilent.

A set of scripts, manuals and patches to make synthesizing and downloading circuits from Logisim Evolution onto the Basys3 FPGA board on Linux easier and more seamless.

CE264 for University of Essex

Here we are implementing Risc-V single cycle microprocessor on Basys3 (Artix-7) .We are testing with Fibonaccie Series and showing on 7 segment display..

Digital Clock for the Basys 3 FPGA

A Sound and Sight Entertainment System (SSES) implemented on Basys3 FPGA Board

FPGA Implementation of Full Search Block matching using an asynchronous handshake based FSM.

A tetris-game on screen using verilog.

Basys 3 driver for a Raspberry Pi NoIR 2.1 camera - COMPE470L class project

Contains projects implemented on the Basys3 board via Vivado (Verilog)

An cellular automata game for a 8x8 matrix on the BetiBoard. (requires Basys3 board)

A FPGA implementation of Ben Eater's SAP-1 computer using the Digilent's BASYS 3 board.

Minimalist 8 bit multicycle RISC CPU

A mini-game system implemented in C for a Basys Board 🕹 🔌 (2018)