Search results

cptra_ss_rdc_clk_cg_o is not gated before cptra_ss_rst_b_o，mismatch intergation spec

Status: Open.

Questions

#1230 In chipsalliance/caliptra-ss;

· cory-chiang opened on Jul 29, 2026

Tool version updates expected for 2.2

Status: Open.

#1229 In chipsalliance/caliptra-ss;

· russellames opened on Jul 24, 2026

[RFC] OCP Recovery Interface: Log reading over Indirect FIFO not supported by I3C Core HW

Future

RFCRequest for Comment - Contributor proposal to develop Caliptra changesRequest for Comment - Contributor proposal to develop Caliptra changes

Status: Open.

Feature

#1228 In chipsalliance/caliptra-ss;

· apatil-26 opened on Jul 22, 2026

The relationship between SRAM groups and clocks

Status: Open.

#1227 In chipsalliance/caliptra-ss;

· cory-chiang opened on Jul 22, 2026

Toggle coverage holes at MLDSA signals

Status: Open.

#1226 In chipsalliance/caliptra-ss;

· chelsea85 opened on Jul 21, 2026

VENDOR_REVOCATIONS_PROD_PARTITION lacks a volatile write lock

Status: Open.

#1224 In chipsalliance/caliptra-ss;

· avifishman opened on Jul 21, 2026

Request: consolidated integration requirements table for Caliptra Subsystem, analogous to "Table 19: SoC integration requirements"

documentationImprovements or additions to documentationImprovements or additions to documentation

Status: Open.

Questions

#1223 In chipsalliance/caliptra-ss;

· anthonybrist opened on Jul 20, 2026

Test enhancement PR tracking

Status: Open.

#1218 In chipsalliance/caliptra-ss;

· russellames opened on Jul 15, 2026

Which is responsible for In RAW, TEST_LOCKED, SCRAP and INVALID states, Caliptra “Core” is not brought out of reset.

Status: Open.

#1217 In chipsalliance/caliptra-ss;

· kartd0122133 opened on Jul 14, 2026

caliptra_ss_fuse_ctrl_test_unlocked0_prov of test_suites fail

Status: Open.

#1214 In chipsalliance/caliptra-ss;

· dark19901121 opened on Jul 7, 2026

[dv] Port block-level design verification for uart block.

Status: Open.

#1212 In chipsalliance/caliptra-ss;

· moidx opened on Jul 2, 2026

·  

2.2 Subsystem RTL

[dv] Port block-level design verification for spi_host block.

Status: Open.

#1211 In chipsalliance/caliptra-ss;

· moidx opened on Jul 2, 2026

·  

2.2 Subsystem RTL