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Pull requests: chipsalliance/caliptra-ss
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[UVM][SPI_HOST] Migrate spi_host UVM DV from OpenTitan to Caliptra with AXI4
#1222
opened Jul 20, 2026 by
samipmodi323
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Draft
[TB] Enable PULP AXI crossbar alongside Avery AXI interconnect VIP in subsystem TB
#1204
opened Jun 29, 2026 by
thommythomaso
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[RTL] Add and integrate UART into Caliptra subsystem
#1203
opened Jun 29, 2026 by
thommythomaso
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[RTL] Add and integrate SPI host controller into Caliptra subsystem
pipeline-run
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#1202
opened Jun 29, 2026 by
thommythomaso
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[TB] Add JTAG test to exhaustively test LCC state transitions
#1185
opened Jun 23, 2026 by
mtdudek
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[TB] Add test to exhaustively test LCC state transitions
#1184
opened Jun 23, 2026 by
mtdudek
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NWP Phase 1: ENABLE_NWP-gated Network Coprocessor + VCS testbench + tests
#1165
opened Jun 5, 2026 by
zahralak
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3 tasks
[DOC] Add table of named/numbered integration requirements
documentation
Improvements or additions to documentation
Trademark
Questions and changes related to Caliptra Trademark.
#1093
opened Mar 17, 2026 by
calebofearth
Collaborator
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Add full I3C AXI RI flow with 3 images and various sizes
#1064
opened Mar 6, 2026 by
clayton8
Collaborator
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[RTL] Update caliptra-rtl to pull axi_if updates and make new signal connections
#1063
opened Mar 4, 2026 by
calebofearth
Collaborator
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