All

122 repositories

caliptra-mcu-sw
Public
Caliptra MCU Software
Rust
•
Apache License 2.0
•77•37•175•67•Updated Jul 27, 2026Jul 27, 2026
Cores-VeeR-EL2
Public
VeeR EL2 Core
fpga processor riscv
fpga processor riscv rtl risc-v open-source-hardware fusesoc verilator riscv32 western-digital
SystemVerilog
•
Apache License 2.0
•107•342•44•10•Updated Jul 27, 2026Jul 27, 2026
caliptra-rtl
Public
HW Design Collateral for Caliptra RoT IP
SystemVerilog
•
Apache License 2.0
•100•148•110•58•Updated Jul 27, 2026Jul 27, 2026
verilator
Public
Verilator open-source SystemVerilog simulator and lint system
SystemVerilog
•
Other
•862•43•0•0•Updated Jul 27, 2026Jul 27, 2026
chisel
Public
Chisel: A Modern Hardware Design Language
scala chip-generator chisel
scala chip-generator chisel rtl chisel3 firrtl verilog
Scala
•
Apache License 2.0
•652•4.7k•356•158•Updated Jul 27, 2026Jul 27, 2026
caliptra-sw
Public
Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test
Rust
•
Apache License 2.0
•116•163•227•83•Updated Jul 27, 2026Jul 27, 2026
sv-tests-results
Public
Output of the sv-tests runs.
HTML
•8•10•0•0•Updated Jul 27, 2026Jul 27, 2026
mjolnir
Public
Mjolnir: AI Vulnerability Scanning Infrastructure
Python
•
Apache License 2.0
•6•3•0•4•Updated Jul 26, 2026Jul 26, 2026
Surelog
Public
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Window…
parser linter preprocessor
parser linter preprocessor antlr verilog python-api systemverilog uvm elaboration vpi
C++
•
Apache License 2.0
•86•468•47•4•Updated Jul 25, 2026Jul 25, 2026
sv-tests
Public
Test suite designed to check compliance with the SystemVerilog standard.
rtl verilog systemverilog
rtl verilog systemverilog hdl compliance-testing symbiflow
SystemVerilog
•
ISC License
•98•383•45•25•Updated Jul 25, 2026Jul 25, 2026
chips-alliance-website
Public
SCSS
•
MIT License
•7•5•4•1•Updated Jul 24, 2026Jul 24, 2026
tac
Public
CHIPS Alliance Technical Advisory Council
Apache License 2.0
•25•9•37•3•Updated Jul 24, 2026Jul 24, 2026
usb2
Public
USB core
VHDL
•
Apache License 2.0
•1•1•0•0•Updated Jul 23, 2026Jul 23, 2026
caliptra-ss
Public
HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.
security rot ocp
security rot ocp root-of-trust caliptra opencomputeproject
SystemVerilog
•
Apache License 2.0
•53•47•79•33•Updated Jul 23, 2026Jul 23, 2026
Caliptra
Public
Caliptra IP and firmware for integrated Root of Trust block
Apache License 2.0
•72•442•114•15•Updated Jul 23, 2026Jul 23, 2026
adams-bridge
Public
Post-Quantum Cryptography IP Core (Crystals-Dilithium)
cryptography digital-signature lattice
cryptography digital-signature lattice pqc ml-dsa-87
SystemVerilog
•
Apache License 2.0
•15•59•16•6•Updated Jul 22, 2026Jul 22, 2026
caliptra-infra
Public
Various tools used for Caliptra's Continuous Integration flows
SystemVerilog
•
Apache License 2.0
•6•3•6•3•Updated Jul 22, 2026Jul 22, 2026
caliptra-dpe
Public
High level module that implements DPE and defines high-level traits that are used to communicate with the crypto peripherals and PCRs
Rust
•
Apache License 2.0
•36•26•12•8•Updated Jul 22, 2026Jul 22, 2026
t1
Public
Scala
•
Apache License 2.0
•48•319•19•36•Updated Jul 22, 2026Jul 22, 2026
UHDM
Public
Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. U…
serialization listener systemverilog
serialization listener systemverilog ieee-standard vpi-api vpi-interface
C++
•
Apache License 2.0
•44•264•14•0•Updated Jul 22, 2026Jul 22, 2026
chisel-nix
Public
Nix template for the chisel-based industrial designing flows.
Nix
•7•58•1•1•Updated Jul 21, 2026Jul 21, 2026
Cores-VeeR-EH2
Public
VeeR EH2 core
SystemVerilog
•
Apache License 2.0
•66•274•12•2•Updated Jul 20, 2026Jul 20, 2026
verible
Public
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
productivity parser formatter
productivity parser formatter analysis style-linter linter language-server-protocol syntax-tree lexer yacc
C++
•
Other
•298•1.9k•572•46•Updated Jul 19, 2026Jul 19, 2026
caliptra-web
Public
Python
•
Apache License 2.0
•10•1•0•0•Updated Jul 17, 2026Jul 17, 2026
caliptra-libspdm
Public
C
•
BSD 3-Clause "New" or "Revised" License
•0•0•0•3•Updated Jul 17, 2026Jul 17, 2026
i3c-core
Public
SystemVerilog
•
Apache License 2.0
•34•54•11•13•Updated Jul 16, 2026Jul 16, 2026
guineveer
Public
https://chipsalliance.github.io/guineveer/
C
•
Apache License 2.0
•5•10•0•0•Updated Jul 16, 2026Jul 16, 2026
Cores-VeeR-EH1
Public
VeeR EH1 core
fpga processor riscv
fpga processor riscv rtl risc risc-v open-source-hardware fusesoc verilator riscv32
SystemVerilog
•
Apache License 2.0
•241•957•20•7•Updated Jul 16, 2026Jul 16, 2026
firrtl-spec
Public
The specification for the FIRRTL language
TeX
•32•66•27•18•Updated Jul 12, 2026Jul 12, 2026
.github
Public
Organization profile for CHIPS Alliance
1•0•2•0•Updated Jul 8, 2026Jul 8, 2026

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CHIPS Alliance

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122 repositories

caliptra-mcu-sw

Cores-VeeR-EL2

caliptra-rtl

verilator

chisel

caliptra-sw

sv-tests-results

mjolnir

Surelog

sv-tests

chips-alliance-website

tac

usb2

caliptra-ss

Caliptra

adams-bridge

caliptra-infra

caliptra-dpe

t1

UHDM

chisel-nix

Cores-VeeR-EH2

verible

caliptra-web

caliptra-libspdm

i3c-core

guineveer

Cores-VeeR-EH1

firrtl-spec

.github

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Repositories list

122 repositories