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Feat/zvbb bitmanip #465

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b0e05ec
[hardware] Add crypto extension parametrization scaffold
micprog Jun 8, 2026
e98d801
[hardware] Add Zvkb vector crypto bit-manipulation extension
micprog Jun 8, 2026
8365c78
[hardware] Add Zvbb vector basic bit-manipulation extension
micprog Jun 8, 2026
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6 changes: 3 additions & 3 deletions apps/common/runtime.mk
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Original file line number Diff line number Diff line change
Expand Up @@ -79,8 +79,8 @@ RISCV_SIM ?= $(ISA_SIM_INSTALL_DIR)/bin/spike
RISCV_SIM_MOD ?= $(ISA_SIM_MOD_INSTALL_DIR)/bin/spike
# VLEN should be lower or equal than 4096 because of spike restrictions
vlen_spike := $(shell vlen=$$(grep vlen $(ARA_DIR)/config/$(config).mk | cut -d" " -f3) && echo "$$(( $$vlen < 4096 ? $$vlen : 4096 ))")
RISCV_SIM_OPT ?= --isa=rv64gcv_zfh_zvfh_zvl$(vlen_spike)b
RISCV_SIM_MOD_OPT ?= --isa=rv64gcv_zfh_zvfh_zvl$(vlen_spike)b -d
RISCV_SIM_OPT ?= --isa=rv64gcv_zfh_zvfh_zvbb_zvl$(vlen_spike)b
RISCV_SIM_MOD_OPT ?= --isa=rv64gcv_zfh_zvfh_zvbb_zvl$(vlen_spike)b -d

# Python
PYTHON ?= python3
Expand All @@ -100,7 +100,7 @@ DEFINES += $(ENV_DEFINES) $(MAKE_DEFINES)
RISCV_WARNINGS += -Wunused-variable -Wall -Wextra -Wno-unused-command-line-argument # -Werror

# LLVM Flags
LLVM_FLAGS ?= -march=rv64gcv_zfh_zvfh -mabi=$(RISCV_ABI) -mno-relax -fuse-ld=lld
LLVM_FLAGS ?= -march=rv64gcv_zfh_zvfh_zvbb -mabi=$(RISCV_ABI) -mno-relax -fuse-ld=lld
LLVM_V_FLAGS ?= -fno-vectorize -mllvm -scalable-vectorization=off -mllvm -riscv-v-vector-bits-min=0 -mno-implicit-float
RISCV_FLAGS ?= $(LLVM_FLAGS) $(LLVM_V_FLAGS) -mcmodel=medany -I$(CURDIR)/common -O3 -ffast-math -fno-common -fno-builtin-printf $(DEFINES) $(RISCV_WARNINGS)
ifeq ($(LINUX),1)
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4 changes: 2 additions & 2 deletions apps/riscv-tests/isa/Makefile
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Expand Up @@ -43,7 +43,7 @@ RISCV_LLVM ?= clang -fuse-ld=lld
RISCV_CC_OPTS ?= -mcmodel=medany -fvisibility=hidden -mno-relax -nostdlib -nostartfiles
RISCV_CC_OPTS_C ?= -O2 -mno-relax -nostdlib -nostartfiles -fno-vectorize -mllvm -scalable-vectorization=off -mllvm -riscv-v-vector-bits-min=0 -mno-implicit-float
RISCV_CC_DEFS_C ?= $(ARA_DEFINES)
LLVM_V_VERSION ?= v_zfh_zvfh
LLVM_V_VERSION ?= v_zfh_zvfh_zvbb

# Original objdump + spike variables
RISCV_OBJDUMP ?= llvm-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data
Expand All @@ -64,7 +64,7 @@ vpath %.S $(src_dir)
$(RISCV_SIM) --isa=rv32gcv $< 2> $@

%.cout: %
$(RISCV_SIM) --isa=rv64gcv_zfh_zvfh_zvl4096b $< 2> $@
$(RISCV_SIM) --isa=rv64gcv_zfh_zvfh_zvbb_zvl4096b $< 2> $@

%.cout32: %
$(RISCV_SIM) --isa=rv32gcv $< 2> $@
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2 changes: 2 additions & 0 deletions apps/riscv-tests/isa/rv64uv/Makefrag
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Expand Up @@ -180,6 +180,8 @@ rv64uv_sc_tests = vaadd \
vle_vse_hazards \
vfrec7 \
vfrsqrt7 \
zvkb \
zvbb \
vrgather \
vcompress

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